Dual-Field Multiplier Architecture for Cryptographic Applications

The multiplication operation in finite fields GF (p) and GF (2) is the most often used and timeconsuming operation in the harware and software realizations of public-key cryptographic systems, particularly elliptic curve cryptography. We propose a new hardware architecture for fast and efficient execution of the multiplication operation in this paper. The proposed architecture is scalable, i.e., can handle operands of any size; only limited by input/output and scratch space size, not by computational unit. It can also be configured to fit the available chip area for the desired performance. Our proposed architecture computes multiplication faster in GF (2) than GF (p), which conforms with premise of GF (2) for hardware realizations.